Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers

This paper presents a detailed empirical study and analytical derivation of voltage wave-form and energy dissipation of global lines driven by CMOS drivers. It is shown that at high clock frequencies where the output voltage at the termination point of the transmission line L R C Optimizing the Energy-Delay-Ringing Product in On-Chip CMOS Line Drivers Payam Heydari Department of Electrical and Computer Engineering University of California, Irvine, CA 92697 [email protected] Soroush Abbaspour and Massoud Pedram Department of Electrical Engineering-Systems University of Southern California, Los Angeles, CA 90089 {sabbaspo, pedram}@usc.edu 1 may not reach its steady state value during the clock period, it is possible to reduce energy dissipation while meeting a DC noise margin by driver sizing. This is in sharp contrast with the steady state analysis, which states that driver size has no impact on the energy dissipation per output change. In addition, we propose a new design metric which is the product of energy, delay and some measure of ringing in lossy transmission lines. In particular, this paper provides closed-form expressions for the energy dissipation, 50% propagation delay and the percentage of maximum undershoot when the circuit exhibits an under-damped behavior. This metric is used during the driver sizing problem formulation for minimum energy-delay-ringing product.